1. Field of the Invention
The present invention relates to a memory control apparatus connected with a plurality of bus masters and a plurality of memories, and more particularly, relates to a memory control apparatus and a memory control method for, in the case of competing memory accesses, controlling the priorities of those memory accesses.
2. Description of the Related Art
Recent large-scale integration (LSI) circuits have included, on the chip, many information processors (IPs) in addition to a central processing unit (CPU), to achieve higher functionality. In systems including such an LSI circuit, since individual IPs simultaneously process data, a high-capacity high-speed memory is often mounted on the system substrate together with the LSI circuit.
Synchronous dynamic random access memory (SDRAM) devices, for example, have been used as memory devices. Nowadays, to enable faster access, a plurality of high-speed memory devices, such as double data rate (DDR)-SDRAMs, DDR2-SDRAMs, and DDR3-SDRAMs, are sometimes employed.
On the other hand, mainly in battery-powered systems, various efforts are made to reduce power consumption within the entire system. For example, memory devices have a low power consumption mode, so that the memories shift to the low power consumption mode when there is no memory access, and power consumption in the memory devices can be reduced.
To achieve power savings, a memory control apparatus needs to control memory access to extend periods of time during which the memories are placed in the low power consumption mode.
For example, Japanese Patent Application Laid-Open No. 8-153065 discusses a method for, when the priorities of memory accesses need to be changed by monitoring the states of memories (slaves), changing the priorities of transfer requests from a plurality of bus masters by monitoring the states of the memories (slaves). In Japanese Patent Application Laid-Open No. 8-153065, it is determined whether each slave is in a state in which the slave can readily process a transfer request from a bus master. A transfer request to the slave that has been determined not to be able to readily perform processing is masked. Then the transfer is accepted from among the transfer requests to the slave that has been determined to be able to readily perform processing.
There is a memory control apparatus that controls a memory, such as a DRAM, connected externally of a chip as one of slave modules in a system. Such a memory control apparatus of the DRAM has a function for converting a memory access from a bus master to a protocol for the connected DRAM to issue the memory access. Some memory control apparatuses also have a function for controlling a power mode of an external DRAM. As a configuration for implementing a memory control circuit having the function for controlling the power mode of an external DRAM, there is a memory control circuit which explicitly receives the designation of the power mode from the system, and issues a power mode control command for bringing the DRAM into a power-down mode or for turning in and out of a self-refresh mode.
In this case, the explicit designation from the system makes fine control difficult. On the other hand, there is a memory control apparatus that have a function for automatically controlling a power supply mode according to the presence or absence of a memory access received from a bus master. More specifically, such a memory control apparatus functions as follows. When there is no transfer request from the bus master, the memory control apparatus places the memory in a power saving mode. When a transfer request is made to the memory placed in the power saving mode, the memory control apparatus returns the memory from the power saving mode to the normal state in which memory access is available.
The conventional arbitration method is performed based on the assumption that the state of the slave automatically changes from a “not readily available” state to a “readily available” state.
In such a memory control apparatus, if “the state in which a slave can readily process a transfer request from a bus master” is replaced by “the state in which a memory is placed in the power saving mode”, then an access to the memory placed in the power saving mode will be masked. In other words, the memory access will be masked although the memory access can be issued if the memory returns from the power saving mode.
If the access to the memory device placed in the power saving mode is masked, the memory being in the power saving mode remains in that power saving mode. Hence, no memory transfer is performed.
On the other hand, if “the state in which the memory is placed in the power saving mode” is replaced by “the state in which the slave cannot readily process a request from the bus master”, then memory access to the memory device placed in the power saving mode will not be masked. However, depending on the order in which the memory accesses are issued, a time period during which the memory is placed in the power saving mode is shortened, and the power saving becomes less effective.